ende komponent;
komponent shiftersright_stage4 er
Port (in35: i STD_LOGIC_VECTOR (7 downto 0);
stage4right: i STD_LOGIC;
out20: ud STD_LOGIC_VECTOR (7 downto 0));
ende komponent;
begynde
shiftright0: shiftersright_stage1 port kort (D, E
(0), signa15)
shiftright1: shiftersright_stage2 port kort (signa15, E (1 ), signa16),
shiftright2: shiftersright_stage4 port kort (signa16, E
(2), zact),
decideret
zeroact
, når zact = "00000000"
ellers '0';
ende strukturelle;